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<title>CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers </title></head>
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<h1>CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers</h1>
<table>
<tr>
<th>Opcode Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>F2 0F E6 /r CVTPD2DQ xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1.</td></tr>
<tr>
<td>VEX.128.F2.0F.WIG E6 /r VCVTPD2DQ xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1.</td></tr>
<tr>
<td>VEX.256.F2.0F.WIG E6 /r VCVTPD2DQ xmm1, ymm2/m256</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Convert four packed double-precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1.</td></tr>
<tr>
<td>EVEX.128.F2.0F.W1 E6 /r VCVTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 subject to writemask k1.</td></tr>
<tr>
<td>EVEX.256.F2.0F.W1 E6 /r VCVTPD2DQ xmm1 {k1}{z}, ymm2/m256/m64bcst</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 subject to writemask k1.</td></tr>
<tr>
<td>EVEX.512.F2.0F.W1 E6 /r VCVTPD2DQ ymm1 {k1}{z}, zmm2/m512/m64bcst{er}</td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 subject to writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Converts packed double-precision floating-point values in the source operand (second operand) to packed signed doubleword integers in the destination operand (first operand).</p>
<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (2<sup>w-1</sup>, where w represents the number of bits in the destination format) is returned.</p>
<p>EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-tionally updated with writemask k1. The upper bits (MAX_VL-1:256/128/64) of the corresponding destination are zeroed.</p>
<p>VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.</p>
<p>VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are zeroed.</p>
<p>128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.</p>
<p>VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.</p>
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<h3>Figure 3-12.  VCVTPD2DQ (VEX.256 encoded version)</h3>
<h2>Operation</h2>
<p><strong>VCVTPD2DQ (EVEX encoded versions) when src operand is a register</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    k (cid:197) j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] (cid:197)
              Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL/2] (cid:197) 0</pre>
<p><strong>VCVTPD2DQ (EVEX encoded versions) when src operand is a memory source</strong></p>
<pre>(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j (cid:197) 0 TO KL-1
    i (cid:197) j * 32
    k (cid:197) j * 64
    IF k1[j] OR *no writemask*
         THEN
              IF (EVEX.b = 1)
                    THEN
                         DEST[i+31:i] (cid:197)
              Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
                    ELSE
                         DEST[i+31:i] (cid:197)
              Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
              FI;
         ELSE
              IF *merging-masking*
                                                         ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE
                                                         ; zeroing-masking
                         DEST[i+31:i] (cid:197) 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL/2] (cid:197) 0</pre>
<p><strong>VCVTPD2DQ (VEX.256 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[95:64] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])
DEST[127:96] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)
DEST[MAX_VL-1:128](cid:197)0</pre>
<p><strong>VCVTPD2DQ (VEX.128 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[MAX_VL-1:64](cid:197)0</pre>
<p><strong>CVTPD2DQ (128-bit Legacy SSE version)</strong></p>
<pre>DEST[31:0] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] (cid:197)Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[127:64] (cid:197)0
DEST[MAX_VL-1:128] (unmodified)</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);</p>
<p>VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);</p>
<p>VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);</p>
<p>VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);</p>
<p>VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);</p>
<p>VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);</p>
<p>VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);</p>
<p>VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);</p>
<p>VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);</p>
<p>VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);</p>
<p>VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)</p>
<p>CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Invalid, Precision</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 2; additionally</p>
<table class="exception-table">
<tr>
<td>EVEX-encoded instructions, see Exceptions Type E2.</td></tr>
<tr>
<td>If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.</td></tr></table></body></html>